1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit memories, and more particularly to a semiconductor integrated circuit memory which operates in synchronism with a clock and a method for controlling a data bus of such a semiconductor memory.
Recently, it has been required to semiconductor memory devices such as DRAM (Dynamic Random Access Memory) devices input and output data at higher frequencies in accordance with speeding up of CPUs so that the data transfer rate can be increased.
An SDRAM (Synchronous DRAM) device can operate at a high speed in synchronism with a clock signal supplied from the outside.
2. Description of the Related Art
A description will now be given of a conventional data bus control method for SDRAMs.
FIG. 1 illustrates a circuit configuration of a periphery of a memory cell of the SDRAM. The circuit shown in FIG. 1 includes a capacitor 201, NMOS (N-channel Metal Oxide Semiconductor) transistors 212, 223 and 224, and PMOS (P-channel MOS) transistors 213, 221 and 222. The PMOS transistors 221 and 222 and the NMOS transistors 223 and 223 form a sense amplifier 220.
The capacitor 201, which forms a memory cell, can store one-bit data. The data stored in the capacitor 201 is read onto a pair of data bus lines DB and /DB as follows.
The circuit shown in FIG. 1 is supplied with clock signals CK and /CK, a control signal (R (read) or W (write); R is used in this case), and address signals (including a row address and a column address). The control signal R is decoded within the SDRAM device, and results in a row address strobe signal /RAS and a column address strobe signal /CAS. The row address strobe signal /RAS selects one row system in a core circuit of the SDRAM device, that is, a word line. The column address strobe signal /CAS selects one column system in the core circuit, that is, the sense amplifier 220 shown in FIG. 1. The core circuit has a plurality of memory cells arranged in a matrix formation, and each column is provided with a respective sense amplifier such as the sense amplifier 220. Hence, the sense amplifier 220 can sense data read from the memory cells connected to the selected word line.
When the signal /RAS is input, a bit line transfer signal BLT0 is switched to a low level. At this time, a bit line transfer signal BLT1 is at a high level, and the NMOS transistors 203 and 204 are both ON. Thus, the bit lines BL and /BL become connected to the sense amplifier 220. Simultaneously, a precharge signal PR is switched to the low level, and the bit line BL is released from a precharged state.
A sub-word line select signal SW is activated and is thus set to the high level, so that the corresponding word line can be selected. Hence, the NMOS transistor 202, which functions as a cell gate, is made to conduct, and the data stored in the capacitor 201 is read to the bit line BL therefrom.
Then, sense amplifier drive signals SA1 and SA2 are activated, and the NMOS transistors 212 and 213 are thus made to conduct. In that state, the pieces of data on the bit lines BL and /BL are read by the sense amplifier 220 via the NMOS transistors 203 and 204, respectively. The sense amplifier 220 amplifies the pieces of data on the bit lines BL and /BL, so that the potential difference (amplitude) can be increased.
Then, a column line select signal CL is switched to the high level by the signal /CAS, and one of the columns is selected. The NMOS transistors 210 and 211, which function as column gates, are turned ON, and the amplified pieces of data on the bit lines BL and /BL are read to the data bus lines DB and /DB, respectively.
Thereafter, a precharge command is input, and a precharge signal PR is switched to the high level at an appropriate timing. Thus, the NMOS transistors 207, 208 and 209 are turned ON, and the bit lines BL and /BL are thus precharged to a given potential VPR. Hence, the bit lines BL and /BL are reset, and are ready to receive the next control signal (read (R) or write (W)).
At the time of writing data into the selected cell, the sequence reverse to the above-mentioned read sequence is performed. Hence, pieces of data on the data bus lines DB and /DB are stored in the capacitor 201.
A description will now be given, with reference to FIGS. 2 through 8, of a read operation and a write operation of the conventional SDRAM.
FIG. 2 is a timing chart of an operation in which data read operations are successively performed in a single-bank arrangement or the same bank in a multi-bank arrangement. It is assumed that read comments R0, R1 and R2, which are control signals, respectively select mutually different word lines.
In order to read data related to a different row address (different word line) in a bank, it is necessary to read data of memory cells connected to the selected word line onto pairs of bit lines BL and /BL and to thus precharge the bit lines BL and /BL in advance of the reading. Hence, it is required that the read commands R0, R1 and R2 be applied at given time intervals tRC (equal to, for example, 22 ns). Data read from the memory cells in response to the read command are output when the time (access time) tRAC (equal to, for example, 32 ns) necessary for data to be output after the read command such as R0 is input. The above time can be defined as a latency.
FIG. 3 is a timing chart of an operation in which data write operations are successively performed in the conventional SDRAM (the single-bank arrangement or the same bank in the multi-bank arrangement). It is assumed that write commands W0, W1 and W2 which are the control signals select different word lines.
In order to write data into different row addresses (different word lines) in the bank, the pair of bit lines BL and /BL are precharged, and pieces of data on the bit lines BL and /BL into the memory cell selected by the activated word line. Hence, in this case, the write commands W0, W1 and W2 are input at time intervals tWC (equal to, for example 32 ns) necessary for accepting the write command. Further, write data D01 and D02, write data D11 and D12, and write data D21 and D22 are input at time intervals tWR (equal to, for example, 22 ns) necessary for accepting write data.
FIG. 4 is a timing chart of an operation in which a data read operation is performed and subsequently a data write operation is performed in the conventional SDRAM (the single-bank arrangement or the same bank of the multi-bank arrangement).
Data Q01 and Q02 read by read command R0 is output when the access time tRAC of 32 ns elapses after the read command R0 is input, as in the case shown in FIG. 2. Hence, the write command W0 and write data D01 and D02 are allowed to be input after the data read operation responsive to the read command R0 is completed.
FIG. 5 is a timing chart of an operation in which a data write operation is performed and subsequently a data read operation is performed in the conventional SDRAM (the single-bank arrangement in the present case).
The read command R0 following the write command W0 is input when the time interval tWC (equal to, for example, 32 ns) necessary for accepting the next command and the time interval tWR (equal to, for example, 22 ns) elapse, as in the case shown in FIG. 3. Data Q01 and Q02 read responsive to the read command R0 are output when the access time tRAC of 32 ns necessary for associated data to be read responsive to the read command R0 elapses, as in the case shown in FIG. 2.
FIG. 6 is a timing chart of an operation in which the data read operations are serially performed with regard to different banks in the conventional SDRAM (the multi-bank arrangement in the present case). It is assumed that read commands Ra, Rb, Rc and Rd which are control signals are respectively read commands relate to banks a, b, c and d.
In this case, the banks a-d can operate independently when data are read to the bit lines BL and /BL in the respective banks a-d. Hence, the read commands Ra, Rb, Rc and Rd can successively be input. Read data is output when the access time tRAC of 32 ns elapses after the corresponding read command is input. For example, read data Qa1 is read after the access time of 32 ns starting from the time when the read command R0 is input. That is, a latency occurs which results from the circuit operation of the memory cell periphery, the operation of the sense amplifier and so on. If the same read commands, for example, R0 are successively input (the first and fourth cycles in FIG. 6), it is required to separate the same read commands from each other by at least the time interval tRC (equal to, for example, 22 ns).
FIG. 7 is a timing chart of an operation in which the data write operations are serially performed with regard to different banks in the conventional SDRAM device (the multi-bank arrangement in the present case). It is assumed that write commands Wa, Wb, Wc and Wd which are control signals are respectively write commands related to banks a, b, c and d.
In this case, the banks a-d can operate independently when data are written therein. Hence, the read commands Ra, Rb, Rc and Rd can successively be input. Write data are serially input together with the write commands Wa, Wb, Wc and Wd. If the same write commands, for example, Wa, are successively input (the first and fifth cycles in FIG. 7), it is required to separate the same write commands from each other by at least the time interval tWC (equal to, for example, 32 ns).
FIG. 8 is a timing chart of an operation in which the data write operation and the data read operation are serially performed in the conventional SDRAM (the multi-bank arrangement in the present case).
The data write and read operations correspond to the combination of the operations shown in FIGS. 6 and 7, and the operation of the command is completed and then the operation of the next command is performed.
However, the conventional memory device performing the operations shown in FIGS. 2 through 5 has the following disadvantages.
In the case shown in FIG. 2 in which the data read operations are successively performed, the read command R1 subsequent to the read command R0 cannot be input until the time interval tRC equal to, for example, 22 ns elapses after the read command R0 is input. Further, the data Q01 and Q02 read by the read command R0 is output when the access time tRAC of 32 ns elapses after the read command R0 is input. That is, the latency occurs and the data bus is occupied by the data read operation during the blank or latency period.
In the case shown in FIG. 3 in which the data write operations are successively performed, the write command W1 subsequent to the write command W0 cannot be input until the time interval tWC equal to, for example, 32 ns elapses after the write command W0 is input. Further, write data D11 and D12 associated with the write command W1 cannot be input until the time interval tWR equal to, for example, 22 ns elapses after write data D01 and D02 are input. That is, the latency occurs and the data bus is occupied by the data write operations during the latency period.
In the case shown in FIG. 4 in which the data write operation is performed subsequent to the data read operation, the write command W1 cannot be input until read data Q01 and Q02 are output when the access time tRAC of 32 ns elapses after the read command R0 is input. That is, the data bus is occupied by the read operation during the latency period equal to the access time.
In the case shown in FIG. 5 in which the data write operation is performed and the data read operation is subsequently performed, the read command R0 cannot be input until the time interval tWC equal to, for example, 32 ns elapses after the write command W0 is input and until the time interval tWR equal to, for example, 22 ns elapses after the write data D01 and D02 are input. Hence, the data bus is occupied by the write operation during the latency period.
As described above, in the cases shown in FIGS. 2 through 5, the long latency period occurs during which the data bus is occupied. Hence, the next operation cannot be performed until the long latency period elapses. This prevents speeding up of the data read and write operations.
The same disadvantages as those described above occur in the operations shown in FIGS. 6 through 8. More particularly, in the case shown in FIG. 6 in which the data read operations are serially performed with regard to different banks, read data responsive to the read commands Ra, Rb, Rc and Rd are respectively output when the access time tRAC of 32 ns elapses after these commands are respectively input. Hence, the data bus is occupied by the series of data read operations until the last read data Da1 and Da2 are output after the read command Ra is input.
In the case shown in FIG. 7 in which the data write operations are performed with regard to different banks, the data bus is occupied by the series of data write operations until the time interval tWC equal to, for example, 32 ns elapses from the last write command Wa and until the time interval tWR equal to, for example, 22 ns elapses from write data D01 and D02 are input.
In the case shown in FIG. 8 in which the write and read operations are performed with regard to different banks, the data bus is occupied by the write and read operations until the last read data Qc1 and Qc2 are output after the first write command Wa is input.
The operations shown in FIGS. 6 through 8 are faster than those shown in FIGS. 2 through 5 but have a disadvantage in that the data bus is occupied by each operation. Hence, it is still required to speed up the data read and write operations.